Abstract—The paper presents a new and efficient architecture
for H.264/AVC video encoder control. The architecture of mode
decision and cost estimation module is implemented with the
use of bit-serial arithmetic and provides pipelined processing of
image blocks. The module is designed to support FPGA devices.
It has been shown that the design is capable to perform at a
very low clock speed, thus it is a suitable solution for wireless
communications. The proposed modules have been implemented
in Verilog HDL and synthesized for a Xilinx Virtex II family
device.