The H.264/AVC is the most recent
standard of video compression. In this paper orig-
inal and exible architecture of image reconstruc-
tion block for H.264/AVC decoder is presented. De-
pending on application requirements the proposed
design may be congured as low complexity sim-
ple unit with good performance or as fully pipelined
construction with high performance. The architec-
ture was implemented in Verilog HDL and synthe-
sized and then tested on Xilinx VirtexII family de-
vice. The simulation results indicate that the imple-
mented circuit is capable to process real-time video
at clock close to the image sampling frequency.